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VHDL Design Representation and Synthesis
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VHDL Design Representation and Synthesis (Paperback)

£58.99
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Synopsis

For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.



Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.

DR. JAMES R. ARMSTRONG and DR. F. GAIL GRAY are Professors of Electrical and Computer Engineering at Virginia Tech. Dr. Armstrong teaches graduate and undergraduate courses in computer architecture, HDLs, and logic design. He was a member of the original IEEE standardization committee; authored Chip Level Modeling With VHDL, and co-authored Structured Logic Design With VHDL, both from Prentice Hall. Dr. Gray teaches graduate and undergraduate courses in computer engineering, logic design, hardware description languages, coding theory, fault tolerant computing, testing, and microprocessor system design. His work has been published by IEEE Transactions on Computers; Journal of VLSI Signal Processing for Signal, Image, and Video Technology; Design Automation Conference; the VHDL International Users Forum; and many other leading journals and conferences.

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