Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays

This work covers field programmable gate array

(FPGA)-specific optimizations of circuits computing the multiplication of a

variable by several constants, commonly denoted as multiple constant

multiplication (MCM). These optimizations focus on low resource usage but high

performance. They comprise the use of fast carry-chains in adder-based constant

multiplications including ternary (3-input) adders as well as the integration

of look-up table-based constant multipliers and embedded multipliers to get the

optimal mapping to modern FPGAs. The proposed methods can be used for the

efficient implementation of digital filters, discrete transforms and many other

circuits in the domain of digital signal processing, communication and image

processing.